1. Field of the Invention
The present invention generally relates to a capacitor structure, and more particularly, to a capacitor structure with interconnected dual damascene profiles made from preformed dual damascene structures and a method of manufacturing the same.
2. Description of the Prior Art
For several decades, the miniaturization of CMOS technology has been the most important technology requirements for increasing developing microprocessor performance and Dynamic Random Access Memories (DRAMs) density. Embedded DRAM (eDRAM), thanks to its native high integration density, allows bringing large memory volume close to computing cores and is widely used as a data buffer or cache at system-on-chip (SOC). With a 2× to 3× higher density than standard Static Random Access Memory (SRAM), it provides a competitive solution for many system design challenges: high performance computing, video processing, server applications, gaming, etc.
A DRAM generally includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing a charge (i.e., the bit of information) and an access transistor that provides access to the capacitor during read and write operations. The access transistor is connected between a bit line and the capacitor, and is gated (turned on or off) by a word line signal. During a read operation, the stored bit of information is read from the cell via the associated bit line. During a write operation, a bit of information is stored into the cell from the bit line via the transistor. The cells are dynamic in nature due to leakage, and therefore must be periodically refreshed.
Though DRAM is a competitive solution for system design, the performance of the high-density DRAM has not kept pace with the high-performance microprocessor speed, thereby hindering a system performance improvement. For example, with the migration of process node from 45 nm, 32 nm, 22 nm to even 16 nm node, the necessary capacity volume of the capacitor in DRAM cell must be kept to maintain the performance. The current approach in industry to keep the capacity volume of the capacitor is generally to: 1) increase the capacitor depth; 2) increase the dielectric k value (dielectric constant); or 3) thin down the dielectric thickness. Since the approaches 2) and 3) are susceptible to leakage issue, the best way to keeping capacity volume is by increasing the capacitor depth.
However, either for deep-trench type or stack type eDRAM, the depth of trench for accommodating the capacitor can not go deeper due to the physical limitation of etch process, thus it is difficult to keep the necessary capacity volume while the advanced process node keeps migrating and improving.